Herstellungsverfahren eines lateralen Leistungs-MOSFET

Procédé de fabrication d'un transistor latéral de puissance

Method of manufacturing a lateral power mosfet

Abstract

A method of forming a semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises providing a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a method of manufacturing a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well and with an extended drift region is disclosed.

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Patent Citations (0)

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NO-Patent Citations (2)

    Title
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Cited By (1)

    Publication numberPublication dateAssigneeTitle
    CN-102110712-BJune 27, 2012旺宏电子股份有限公司Lateral power metal oxide semiconductor field effect transistor structure and manufacturing method